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#	Item
721	Facelift: Hiding and Slowing Down Aging in Multicores∗ Abhishek Tiwari and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-09-13 00:18:06 Computer hardware Computer architecture Integrated circuits Microprocessors Electronic design Frequency scaling Microarchitecture Hot carrier injection CPU cache Electronic engineering Electronics Central processing unit
722	Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules ∗ Aditya Agrawal, Amin Ansari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma. Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-14 22:55:13 Computing EDRAM Memory refresh Dynamic random-access memory CPU cache Bloom filter Tile Cache Computer memory Computer hardware Visual arts
723	Scalable   Cache Miss Handling   For High MLP James Tuck, Luis Ceze, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-01-01 23:58:17 Computer engineering Computer memory Microprocessors CPU cache Cache Memory-level parallelism Runahead Intel Core Microarchitecture Computer architecture Computer hardware Central processing unit
724	POSH: A TLS Compiler that Exploits Program Structure ∗ Wei Liu James Tuck Luis Ceze Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-02-05 23:40:10 Parallel computing Central processing unit Software optimization Profiling Superscalar CPU cache Automatic parallelization Compiler optimization Task parallelism Computing Computer hardware Computer architecture
725	Rebound: Scalable Checkpointing for Coherent Shared Memory Rishi Agarwal, Pranav Garg, and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,garg11,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:24:25 Central processing unit Microprocessors Application checkpointing Computer memory Parallel computing CPU cache Multi-core processor AMD 10h Microarchitecture Computer architecture Computer hardware Computing
726	Encyclopedia of Parallel Computing “00170” — [removed] — 12:30 — Page 1 — #2 T  Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-05-19 11:47:48 Computer hardware Concurrent computing Central processing unit Threads CPU cache Multithreading Process Speculative Computing Computer architecture Parallel computing
727	Microsoft PowerPoint - present_micro00 [Compatibility Mode] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-30 23:33:48 Computing Central processing unit Thermodynamics Dynamic random-access memory Dynamic voltage scaling CPU cache Temperature Computer hardware Computer memory Energy conservation
728	Design Trade-Offs in High-Throughput Coherence Controllers Anthony-Trung Nguyen Microprocessor Research Labs Intel Corporation Santa Clara, CA[removed]removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-09-30 19:13:24 CPU cache Cache MESI protocol Parallel computing Computing Cache coherency Computer hardware
729	Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-04-04 17:00:54 Computing Microprocessors Threads Parallel computing CPU cache Computer memory Multithreading Microarchitecture Threading Computer hardware Computer architecture Central processing unit
730	Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors Marcelo Cintra Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:25:05 Computer architecture CPU cache Memory disambiguation Squash Branch predictor Parallel computing Central processing unit Monitor Speculative execution Computer memory Computing Computer hardware

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